Generate HDL-optimized CRC code bits and append to input data
This hardware-friendly CRC Generator System object™, like the CRC Generator System object, generates cyclic redundancy code (CRC) bits. However, the HDL CRC Generator System object is optimized for HDL code generation. Instead of frame processing, the System object processes data at the streaming mode. Control signals are added at both input and output for easy data synchronization.
To generate cyclic redundancy code bits optimized for HDL code generation:
H=comm.HDLCRCGenerator creates an HDL-optimized cyclic redundancy code (CRC) generator System object, H. This object generates CRC bits according to a specified generator polynomial and appends them to the input data.
H = comm.HDLCRCGenerator(Name,Value) creates an HDL-optimized CRC generator System object, H, with additional options specified by one or more Name,Value pair arguments, where Name is a property name and Value is the corresponding value. Name must appear inside single quotes (''). You can specify several name-value pair arguments in any order as Name1,Value1,...,NameN,ValueN.
H = comm.HDLCRCGenerator(POLY,Name,Value) creates an HDL-optimized CRC generator System object, H, with the Polynomial property set to POLY, and the other specified properties set to the specified values.
Sets Polynomial property to POLY at System object construction
Specify the generator polynomial as a binary row vector, with coefficients in descending order of powers. If you set this property to a binary vector, its length must be equal to the degree of the polynomial plus 1. The default is [1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1].
The value with which the CRC checksum is to be XORed just prior to being appended to the input data. This property can be specified as a binary, double or single precision data type scalar or vector. The vector length is the degree of the generator polynomial that you specify in the Polynomial property. When you specify Final XOR Value as a scalar, the object expands the value to a row vector of length equal to the degree of the generator polynomial. The default is 0.
Specify the initial conditions of the shift register as a binary, double or single precision data type scalar or vector. The vector length is the degree of the generator polynomial that you specify in the Polynomial property. When you specify initial conditions as a scalar, the object expands the value to a row vector of length equal to the degree of the generator polynomial. The default is 0.
A logical quantity that specifies whether the output CRC checksum should be flipped around its center after the input data is completely through the shift register. The default is false.
A logical quantity that specifies whether the input data should be flipped on a bytewise basis prior to entering the shift register. The default is false.
|clone||Create HDLCRCGenerator System object with same property values|
|isLocked||Locked status for input attributes and nontunable properties|
|release||Allow property value and input characteristics change|
|reset||Reset states of CRC generator object|
|step||Generate CRC checksums for input message based on control signals and appends checksums to output message|
Encode signal using an HDL-optimized CRC generator.
% Using default polynomial with CRC length 16 hGen = comm.HDLCRCGenerator; % run HDL CRC Generator 6 steps numSteps = 6; % Control signals for all 6 steps startIn = logical([1 0 0 0 0 0]); endIn = logical([0 1 0 0 0 0]); validIn = logical([1 1 0 0 0 0]); % 32 bit data to be encoded, in two 16 by 1 columns msg = randi([0 1],16,2); % random input to HDLCRCGenerator while it is processing the msg randIn = randi([0, 1],16,numSteps-2); dataIn = [msg randIn]; % Run HDL CRC Generator 6 steps % Output data: dataOut % Output Control signals: startOut, endOut, validOut for i = 1: numSteps [dataOut(:,i), startOut(i),endOut(i), validOut(i)] = step(hGen,... dataIn(:,i),startIn(i),endIn(i),validIn(i)); end
Timing diagram for HDL-optimized CRC generator
The HDL CRC Generator System object introduces a latency on the output. This latency can be computed with the following equation:
initialdelay = (CRC length/input data width) + 2